MSP8510 pmc-2031171, issue 4 ? copyright pmc-sierra, inc. 200 6 all rights reserved. proprietary and confidential to pmc-sierra, inc. and for it s customers? internal use. multi-service processor product overview pmc-sierra's msp8500 series multi- service processor products are designed to meet the needs of networ king, storage, office automation, industrial control and high-e nd consumer applications. the MSP8510 multi-service processo r is a highly-integrated, feature- rich product that incorporates pmc-sierra's high performance e9000 microprocessor core. the MSP8510 uses the fast device bus (fdb) as the system bus to interc onnect all the on-chip devices to each other and to the e9000 microprocessor using the generic device interface (gdi). all msp8500 series products provide a variety of interfaces including pci, ethernet, and rom, flash, compact flash, sram, and other low-speed peripheral interfaces. product highlights ? e9000 microprocessor core: ? 600 mhz to 1 ghz operation ? dual-issue superscalar 7-stage pipeline ? 16 kbyte l1 instruction and data caches with parity and a 256- kbyte l2 cache with ecc support ? 8k entry branch prediction table ? multiple reads with out-of-order return ? mmu with 128 total tlb entries, page size range: 4 kbytes to 256 mbytes. ? high-performance floating point unit (ieee 754) ? fixed-point dsp instructions ? 400 mhz fast device bus (f db) system interconnect: ? multiple master, sh ared, on-chip bus ? bus performance monitoring ? connects the e9000 cpu and othe r peripherals to memory and i/o interfaces ? 167 ? 200 mhz ddr1/ddr2 sdram me mory controller with 64-bit data interface: ? supports class i and cla ss ii sstl drive strengths ? supports maximum addressing up to 4 gbytes ? provides ddr2 single-ended dqs signaling so that ddr2 rams may be supported and operated in ddr1 mode ? ddr1 supports device densities of 64, 128, 256, 512 mbits and 1 gbit. ddr2 supports densities of 256 mbits, 512 mbits and 1gbit ? ddr2 supports device widths of 8 and 16 bits. ddr1 additionally supports 32-bit widths ? supports unbuffered and registered dimms ? 2 pci ports, 32 bits each: ? compliant with pci 2.3 standard ? supports 0 to 66 mhz frequencies ? supports on-line inse rtion and removal ? local bus controller providing glue less rom, flash, compact flash, sram, external usb 2.0 devices, and variable-latency i/o (vlio) support: ? 6 independent chip selects block diagram on-chip memory gdi port pci controller pci controller gdi port ddr1/ ddr2 controller gigabit ethernet (ge) subsystem e9000 cpu core ge port 1 ge port 0 gdi port gdi port gdi port gdi port channelized dma controller central processing interface central interrupt controller local bus controller gdi port packet fifo dual uart (duart) twi/ mdio/ mdc gdi port dma controller fast device bus (fdb) central arbiter released product brief
MSP8510 multi-service processor corporate head office: pmc-sierra, inc. mission towers one 3975 freedom circle santa clara, ca, 95054, u.s.a. tel: 1.408.239.8000 fax: 1.408. 492.1157 pmc-2031171 (r4) ? copyright pmc- sierra, inc. 200 6 . all rights reserved. for a complete list of pmc-sierra?s trademarks , visit www.pmc-sierra.com/legal/. othe r product and company names mentioned herein may be the trademarks of their respective owners. for corporate information, send email to: info@pmc-sierra.com. all product documentation is available on our web site at: www.pmc-sierra.com. operations head office: pmc-sierra, inc. 100-2700 production way burnaby, bc v5a 4x1 canada tel: 1.604.415.6000 fax: 1.604.415.6200 ? 2 ethernet mac or generic pack et interfaces (ge subsystem + generic device interface xdma controller): ? ethernet mac interfaces su pport industry-standard tbi (1000 mbit/s), gmii (1000 mbit/s), and mii (10/100 mbit/s, full and half duplex) interface modes ? integrated dma support for ge subsystem: ? up to 16 logical channels for each receive and transmit direction ? receive and transmit are independent ? 32-kbyte scalable packet fifo: ? 24 kbytes for the receive direction. configurable sizing ? support for ethernet pause flow control ? 2 integrated 16550 uart ports ? 32 kbytes of on-chip memory (ecc) ? 64 general-purpose i/o pins with integrated de-bounce on 8 pins ? integrated watchdog timer and 4 general-purpose timers ? up to 4 ports of two-wire interfac e (twi) with support for small form factor plug-able (sfp) or up to 4 ports of mdio/mdc interface protocol through the general-purpose i/o pins ? integrated dma engine, which suppo rts 4 independently configured and controlled channels ? support for 256 vectored interrupts: ? in-band interrupt sources fr om all on-chip gdi devices ? flexible mapping of interrupt ve ctors to e9000 cpu interrupt lines ? integrated on-chip ej tag debug circuitry: ? a dedicated debug module on the e9000 core ? watch exceptions, interrup t and exception debuggers, performance counters, and 64-entry trace buffers ? 896-pin fcbga package, 31 mm x 31 mm ? pin compatible with the msp8520 multi-service security processor applications ? low-end/mid-range enterpr ise switches & routers ? storage networking ? office-in-a-box gateway ? control plane processing ? smb network attached storage (nas) ? imaging systems: colo r laser printers/mfps ? embedded computing ? industrial and general purpose control ? media networked server support operating systems ? open source linux versions 2.4 and 2.6 ? vxworks 5.5 from wind river ? neutrino from qnx software systems ejtag emulators ? wind river ? corelis evaluation boards ? pmc-sierra pm2330-kit reference kit ? atx form-factor evaluation board companion chips ? wide range of companion chips ava ilable to interface with the pci bus control bus ? ? ? fe line card fe fe pci user MSP8510 processor line card fe fe pci user MSP8510 processor asic asic serdes serdes system control/processor card pci switch msp8500 series processor phy phy distributed router an d multi-service switch further resources msp8520 multi-service security processor www.pmc-sierra.com/pro ducts/details/msp8520/ voip network processor chip family www.pmc-sierra.com/voi p-network- processor/ technical documentation www.pmc-sierra.com/documentation/
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